How to pass macro definition from "make" command line arguments (-D) to C source code?

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I usually pass macro definitions from "make command line" to a "makefile" using the option : -Dname=value. The definition is accessible inside the makefile.

I also pass macro definitions from the "makefile" to the "source code" using the similar compiler option : -Dname=value (supported in many compilers). This definition is accessible in the source code.

What I need now, is to allow the user of my makefile to be able to pass arbitrary macro definitions from the "make.exe commandline" to "source code" right away, without having to change anything in the makefile.

so the user can type : make -f -SOMEOPTION var=5

then directly the code main.c can see var :

int main()
  int i = var;

Call make command this way:

make CFLAGS=-Dvar=42

And be sure to use $(CFLAGS) in your compile command in the Makefile. As @jørgensen mentioned , putting the variable assignment after the make command will override the CFLAGS value already defined the Makefile.

Alternatively you could set -Dvar=42 in another variable than CFLAGS and then reuse this variable in CFLAGS to avoid completely overriding CFLAGS.

Passing Parameters: Simple make Macros, Passing Parameters: Simple make Macros. The macro reference acts as a placeholder for a value that you define, either in the makefile itself, or as an argument to the make command. If you then supply make with a definition for the CFLAGS macro, make replaces its references with the value you have defined. macro (array[x = y, x + 1]) passes two arguments to macro: array[x = yand x +1]. If you want to supply array[x = y, x + 1]as an argument,you can write it as array[(x = y, x + 1)], which is equivalent Ccode. All arguments to a macro are completely macro-expanded before they aresubstituted into the macro body.

Call make this way

make CFLAGS=-Dvar=42

because you do want to override your Makefile's CFLAGS, and not just the environment (which has a lower priority with regard to Makefile variables).

Macro Arguments (The C Preprocessor), is performance. They are a way of eliminating function call overhead because they are always expanded in-line, unlike the "inline" keyword which is an often-ignored hint to the compiler, and didn't even exist (in the standard) prior to C99. More complex than object-like macros, a function-like macro definition declares the names of formal parameters within parentheses, separated by commas. An empty formal parameter list is legal: such a macro can be used to simulate a function that takes no arguments. C99 adds support for function-like macros with a variable number of arguments.

Just use a specific variable for that.

$ cat Makefile 
    echo foo | gcc $(USER_DEFINES) -E -xc - 

$ make USER_DEFINES="-Dfoo=one"
echo foo | gcc -Dfoo=one -E -xc - 

$ make USER_DEFINES="-Dfoo=bar"
echo foo | gcc -Dfoo=bar -E -xc - 

$ make 
echo foo | gcc  -E -xc - 

MAKE Macros, To define a macro that uses arguments, you insert parameters between the pair of parentheses in the macro definition that make the macro function-like. Macro definition: Macro usage: Actual code the macro replaces: We can see the ARG1 = 3 is used to form the variable’s name. (I.e. m_mst_3 and mst_3_lcl) 2. “`” “(Tick followed by a double quote) The “`” “ quotation can be used to interpret the argument as a string. Example: Macro Definition: Macro usage: Actual code the macro replaces:

Preprocessor Directives in C language, Macro substitution or Macro , If you wish to define a function-like macro on the command line, write its so that you can pass a file preprocessed with -C to the compiler without problems. Macro Definition ll Calling a Macro ll Expansion of Macro Explained with Examples in Hindi 5 Minutes Engineering Pass-1 Of 2-PASS Assembler Explained with Flowchart ll SPOS ll Explained with

$ cat x.mak
    echo $(OPTION)
$ make -f x.mak 'OPTION=-DPASSTOC=42'
echo -DPASSTOC=42

Why use Macros in C?, I would like to transition from this method to running builds using solely the command line and passing these Macro definitions as arguments to  You can by using macro parameters. Macro parameters enable you to pass values into the macro at macro invocation, and set default values for macro variables within the macro definition. In this blog post, I also discuss how you can pass in a varying number of parameter values. There are two types of macro parameters: positional and keyword.

Macro Arguments (The C Preprocessor), How can I enable #ifdef macro in the command line of "make" (NOTE: I do NOT want to change source code or makefile to define that macro from time to time). Placing commas inside a variable is often a poor idea. If you intend to use it as a macro parameter it will fail because the macro variable resolves with the commas and then each value after a comma is treated as a another parameter.

Preprocessor Options (Using the GNU Compiler Collection (GCC)), This behavior resembles the use of #define with or without a value. The /D option doesn't support function-like macro definitions. To insert  The macro name is replaced by a copy of the macro body. If the macro accepts arguments, the actual arguments following the macro name are substituted for formal parameters in the macro body. The process of replacing a macro call with the processed copy of the body is called expansion of the macro call. In practical terms, there are two types of

Passing Macro Definitions to Makefile in command line, A program may define a macro at one point, remove that definition later, and then provide We pass the -gdwarf-2 and -g3 flags to ensure the compiler includes  This is actually a very good hack – indeed, this would have worked in my original (now abandoned) use case. This of course applies only to the subset of cases where an inner function wants to paste the macro, but there are only three possible cases: the inner function can paste, expand or stringify the macro, and with the latter two it is irrelevant where in the chain the macro is expanded

  • Why the downvote? Looks like a perfectly legitimate question to me.
  • ... and @MemoryLeaks should be cautious and not override CGLAGS in his Makefile, e.g. always use CGLAGS = $(CGLAGS) -Wall.
  • You cannot use "CFLAGS = $(CFLAGS) -Wall"; this would be a recursive definition and make does not allow this. You could use "CFLAGS := $(CFLAGS) -Wall", or "CFLAGS += -Wall", but those won't work either because an assignment on the command line has a higher precedence. You could use "override CFLAGS += -Wall", but generally we recommend you just choose different variables internally. The GNU Coding Standards require CFLAGS etc. be left for the user, and makefiles choose another variable, like "local_CFLAGS = $(CFLAGS) -Wall".
  • Just to add to @MadScientist note, the GNU Coding Standards also state that $(CFLAGS) should come last, so that any options specified by a user will override anything the Makefile sets internally. That would mean using e.g. local_CFLAGS = -Wall $(CFLAGS). Conversely, if there's something you really want to take precedence, put it after $(CFLAGS), as in @MadScientist comment.
  • How to set multiple macros by this?
  • @WoodyHuang for example CFLAGS="-Dvar1=42 -Dvar2=314"
  • the question is to pass arbitrary definitions from the make commandline directly to C source code "without changing the makefile". So I wanted to change my makefile once, to allow for those arbitrary definitions to be made.
  • Doesn't work for make. That is make -DMAKE_DEFINE=11 says invalid option.