How to expand variables after entering custom define that wraps foreach?

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I have many very similar $(foreach..) loops in a makefile that work like in the target_old target below:

define NL


endef
extras=some/path/
vars=a b c

all: target_old target_new

target_old:
        # foreach and some multiple evals inside and some multiple commands inside
        $(foreach var, ${vars}, \
                $(eval extra := ${extras}${var}) \
                @echo var is ${var} and extras is ${extra}$(NL) \
        )


# my try to wrap it in a function
define foreach_vars
        $(foreach var, ${vars},
                $(eval extra := ${extras}${var}) \
                $1$(NL) \
        )
endef

target_new:
        @echo this is wrong:
        $(call foreach_vars, \
                @echo var is ${var} and extras is ${extra} \
        )

I have many multiple such foreach loops with all the same evals inside the foreach. So I wanted to wrap the foreach loop with the evals inside my own function in foreach_vars. So I don't have to $(eval extra := ${extras}${var}) inside each foreach call. I created target_new target to test it. I would want the output from both targets to be the same, make target_old prints:

$ make target_old
var is a and extras is some/path/a
var is b and extras is some/path/b
var is c and extras is some/path/c

However target_new doesn't pick the ${var} from inside the loop, and ${var} just expands to nothing:

$ make target_new
this is wrong:
var is and extras is
var is and extras is
var is and extras is

I guess this is because the expansion happens before entering the $(call...). Is there any method I can use to "defer" the expansion of arguments inside the $(call...) call until inside foreach inside my function? Is is possible to write a custom foreach-like macro in make? Is there just other method used to implement such functionality?

Yes, your problem comes from the expansion(s) that do not happen when you would like and in the order you would like.

Your use of make is quite unusual because you are using make constructs (foreach, eval, call...) in recipes that are normally plain shell. I guess you have a very good reason but wouldn't it be much easier if you were separating the make world and the shell world? Like in the following, for instance:

extras := some/path/
vars   := a b c

target_old:
    @for var in $(vars); do \
       extra=$(extras)$${var}; \
       echo var is $${var} and extra is $${extra}; \
     done

It uses make variables (vars, extras) and shell variables (extra, var). The recipe is plain shell. Note the $$ used to escape the first expansion by make such that the shell expansion ${xxx} is done by the shell. Note also the line continuations (\) that form a single line recipe, despite the look. As each line of a make recipe is executed by a separate shell, this is needed to pass shell variables between commands of the shell script.

If you wish, you can also wrap the shell for loop in a make recursively expanded variable:

for = for var in $(vars); do $(1); done

target_new:
    @$(call for,extra=$(extras)$${var}; echo var is $${var} and extra is $${extra})

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${var} gets immediately expanded, so it needs to be escaped as $${var}. This itself does not fix the issue, since now $1 contains a literal ${var}, which does NOT get expanded within foreach. I would make a simple subst though to get it fixed, e.g.:

$ cat Makefile
define NL


endef
extras=some/path/
vars=a b c

define foreach_vars
        $(foreach var, ${vars},
                $(eval extra := ${extras}${var}) \
                $(subst $$(var),$(var), \
                $(subst $$(extra),$(extra), \
                $(1))) \
                $(NL) \
        )
endef

target_new:
        $(call foreach_vars, \
                @echo var is $$(var) and extras is $$(extra) \
        )

Output:

$ make target_new
var is a and extras is some/path/a
var is b and extras is some/path/b
var is c and extras is some/path/c

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Comments
  • This formulation hides the exit code of the command from make
  • Which formulation? The last one? Did you give it a try, e.g. by adding ; exit 1 at the end of the call parameter? You should.
  • exit 1 is an exception that escapes the running shell. You need to simulate a failing command with (exit 1): $(call for,extra=$(extras)$${var}; echo var is $${var} and extra is $${extra}; (exit 22)) say
  • Ah, I see, sorry, I misunderstood. Yes, you are right, make does not fail if the exit status of the last command of the shell is not 0. Not sure I understand why. But if this is a problem there are probably several ways to fix it, like, for instance, adding ; exit $$? at the end of the for definition. Or adding ` || exit $$?` at the end of the call parameter.
  • man bash says The return status is the exit status of the last command that executes. set -e is often useful
  • Nice! Yes, yes, I thought about it. Never could implement it properly. I think I'll try to go with not splitting the variable definition into a separate line, just in one line with $(eval ). Like such: $(eval command = @echo var is ${var} and extras is ${extra})$(call foreach_vars, command).
  • No reason to put them on the same line. Just write in the most readable way you can. Remember, line breaks are really only important once the expansion has finished, as they delineate separate shell commands.