Difference between 1 and 1'b1 in Verilog

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What is the difference between just giving 1 and giving 1'b1 in verilog code?

The 1 is 32 bits wide, thus is the equivalent of 32'b00000000_00000000_00000000_00000001

The 1'b1 is one bit wide.

There are several places where you should be aware of the difference in length but the one most likely to catch you out is in concatenations. {}

reg [ 7:0] A;
reg [ 8:0] B;
   assign A = 8'b10100101;
   assign B = {1'b1,A};  // B is 9'b110100101
   assign B = {1,A};     // B is 9'b110100101
   assign B = {A,1'b1};  // B is 9'b101001011
   assign B = {A,1};     // B is 9'b000000001 !!!!

what's the difference between writing 1.0 and 1. or 2.0 and 2 , There is not difference in matlab. Sometimes, people like to write "1." instead of 1 to make it easier to port to/from other programming languages later, as it is a� The difference between 1, 01, 001 is 1 has no zeros, but 01 has one zero and 001 has two zeros. Login to reply the answers How do you think about the answers? You can sign in to vote the answer.

So, what's the difference between, say,

logic [7:0] count;
count <= count + 1'b1;


logic [7:0] count;
count <= count + 1;

Not a lot. In the first case your simulator/synthesiser will do this:

i) expand the 1'b1 to 8'b1 (because count is 8 bits wide) ii) do all the maths using 8 bits (because now everything is 8 bits wide).

In the second case your simulator/synthesiser will do this:

i) do all the maths using 32 bits (because 1 is 32 bits wide) ii) truncate the 32-bit result to 8 bits wide (because count is 8 bits wide)

The behaviour will be the same. However, that is not always the case. This:

count <= (count * 8'd255) >> 8;

and this:

count <= (count * 255) >> 8;

will behave differently. In the first case, 8 bits will be used for the multiplication (the width of the 8 in the >> 8 is irrelevant) and so the multiplication will overflow; in the second case, 32 bits will be used for the multiplication and so everything will be fine.

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1'b1 is an binary, unsigned, 1-bit wide integral value. In the original verilog specification, 1 had the same type as integer. It was signed, but its width was unspecified. A tool could choose the width base on its host implementation of the int type.

Since Verilog 2001 and SystemVerilog 2005, the width of integer and int was fixed at 32-bits. However, because of this original unspecified width, and the fact that so many people write 0 or 1 without realizing that it is now 32-bits wide, the standard does not allow you to use an unbased literal inside a concatenation. {A,1} is illegal.

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