Allow Makefile both append and override target

makefile set variable in target
makefile override
makefile target-specific variables
makefile double-colon target
makefile set variable from command
makefile include
makefile define
makefile replace target

I have base Makefile for all my services, in some cases I want to use my default "test" target, in other cases I want to override\add to it. These are the files I have so far (and obviously its not working as expect..).

MakefileBase

test:
    ./.../run-tests.sh

Makefile

BASE_FILE := /path/to/MakefileBase
include ${BASE_FILE}
test:
    @$(MAKE) -f $(BASE_FILE) test # un/comment this line in order to run the default tests.
#   echo "custom test"

When I run the test with the first line commented out I get the following

Makefile:10: warning: overriding commands for target `test'
/.../MakefileBase:63: warning: ignoring old commands for target `test'
echo "no tests"
no tests

except of the warning it works as expected, the problem is when I try to use the parent function then I get the following errors:

Makefile:9: warning: overriding commands for target `test'
/.../MakefileBase:63: warning: ignoring old commands for target `test'
make[1]: test: No such file or directory
make[1]: *** No rule to make target `test'.  Stop.
make: *** [test] Error 2

Actually, both answers so far are wrong or incomplete:

exit 0 in a rule will just exit the current shell (which runs only the exit 0 command, so it is a no-op in this case). So this won't override.

It's not true that you cannot override a command without warning. If it is not necessary that both targets have the same name, you can do:

MakefileBase

.PHONY: test-base
test-base:
    echo base

%: %-base  # handles cases where you don't want to override

Makefile1

include MakefileBase

.PHONY: test
test:
    echo override

Makefile

include MakefileBase

.PHONY: test
test: test-base
    echo append

As with double colon rules, the effects of each targets (on each other) have to be considered, especially if you move away from .PHONY (for example, files considered up-to-date because the other rule just updated them).

BTW, I don't see the problem with your approach (aside from the warning). For me it worked fine.

Override target in makefile to add more commands?, You can write your own clean and make it a preq of the common clean. clean: myclean myclean: rm whatever. Yours will run first. If for some  You can often use the ‘include’ directive to include one in the other, and add more targets or variable definitions. However, it is invalid for two makefiles to give different recipes for the same target.

Hacky, but you can get add, and a limited form of override that can never be deeper than one override. Both use double colon rules.

add: use double colons on both rules

override: use double colons on both rules, appending command exit 0 to the last rule

# "addcmd" echoes "BA", "overridecmd" echoes "B"

addcmd ::
  echo "A"

addcmd ::
  echo "B"

overridecmd ::
  echo "A"

overridecmd ::
  echo "B"
  exit 0

GNU make - How to Use Variables, Appending: How to append more text to the old value of a variable. Override Directive: How to set a variable in the makefile even if the user has set it with a worse, it causes the wildcard and shell functions to give unpredictable results because both are used together in complex ways when doing makefile programming. When we run make, the default target (some_file, since it’s first) will get called. It will first look at its list of dependencies, and if any of them are older, it will first run the targets for those dependencies, and then run itself. The second time this is run, neither target will run because both targets exist.

This is what double-colon rules are for:

test::
        ./.../run-tests.sh

and:

BASE_FILE := /path/to/MakefileBase
include ${BASE_FILE}

test::
        @$(MAKE) -f $(BASE_FILE) test

This will "add to" an existing target. There is no way to override a target with a different recipe without incurring a warning.

If you want to do that the only way is to use variables to hold the recipe then override the variable value. For example:

test_recipe = ./.../run-tests.sh

test:
        $(test_recipe)

and:

BASE_FILE := /path/to/MakefileBase
include ${BASE_FILE}

test_recipe = @$(MAKE) -f $(BASE_FILE) test

Makefile Tutorial by Example, The second time this is run, neither target will run because both targets exist. some_file: Simply expanded allows you to append to a variable. Recursive  6.7 The override Directive. If a variable has been set with a command argument (see Overriding Variables), then ordinary assignments in the makefile are ignored.If you want to set the variable in the makefile even though it was set with a command argument, you can use an override directive, which is a line that looks like this:

[PDF] GNU Make, 3.6 Overriding Part of Another Makefile 16 6.6 Appending More Text to Variables. fact, each '.o' file is both a target and a prerequisite. and may also give a recipe to use to create or update the targets. Target-specific variables have the same priority as any other makefile variable. Variables provided on the command line (and in the environment if the ‘-e’ option is in force) will take precedence. Specifying the override directive will allow the target-specific variable value to be preferred.

Linux Kernel Makefiles, Makefile the top Makefile. .config the kernel configuration file. can be used and if both a 'Makefile' and a 'Kbuild' file exists, then the 'Kbuild' file will be used. Duplicates in the lists are allowed: the first instance will be linked into built-in.a $(obj) is a relative path which points to the directory where the target is saved. This appendix provides some basic information about the make utility, makefiles, and makefile macros. It also refers you to dialog boxes in Sun WorkShop that allow you to set makefile options and to add, delete, and override makefile macros. The make Utility. The make utility applies intelligence to the task of program compilation and linking.

make(1) manual page, V, Force the -V option to print raw values of variables, overriding the default behavior set via .MAKE. If used, this feature allows make to easily search in the current source tree for Rather than re-building a target as specified in the makefile, create it or update its +=, Append the value to the current value of the variable. Add a help target to a Makefile that will allow all targets to be self documenting - Makefile

Comments
  • It only adds the commands, if I try to add test:: echo "I want to do nothing at all" It will run the the command from the base make file and than echo